High Dynamic Range Modulo ADC

Analog-to-Digital Converters (ADCs) play a vital role in modern information processing systems. A practical bottleneck of an ADC is its Dynamic Range (DR), say [-λ, λ]. Specifically, if the input (to the ADC) signal's DR is beyond that of the ADC's, then the signal is clipped, which is undesirable in many applications. ADC's DR should be sufficiently high to avoid clipping, which leads to high power consumption.

                                       

Modulo-ADC is one of the techniques used to address the DR issue, where we preprocess the input signal using a non-linear modulo operator. Specifically, whenever the signal's amplitude goes beyond the ADC’s DR, a folding operation is performed using the modulo operator such that the amplitude of the resultant folded signal is within [-λ,λ]. Then, samples of the folded signal are measured through a conventional ADC with low DR. During reconstruction, the true samples are recovered from the folded ones by using an unfolding algorithm. 

Handling High DR Band-Limited Signals

In this demo, we present a dedicated hardware prototype that can handle high DR input signals. Furthermore, we propose several new algorithms for unfolding. Our algorithms enable robust recovery from modulo samples at the minimal possible rate, slightly above the Nyquist rate. The proposed algorithms use the time-domain separation and Fourier-domain separation properties of the given finite energy bandlimited signal. Through simulation and hardware results we compare the pros and cons of the proposed algorithms. We present the hardware demonstration together with an interactive Graphical User Interface (GUI).

1. Algorithms

 

 

 

 

 

 

Comparison Between Algorithms

All algorithms aim to recover the true samples by estimating the residual signal:

  • B2 R2 estimates the residual signal by solving an optimization problem using a projected gradient descent algorithm
  • LASSO B2 R2 estimates the residual signal by formulating the problem as a sparse recovery problem.

2. Hardware

Working Principle:

The principle of computing a modulo signal, (t), from an input signal, is shown by the block diagram in Figure 4. The system comprises an adder S, a Direct-Voltage Generator (DVG), and two comparators, Comp-1 and Comp-2. To understand the working flow, let us first assume that for some time instant t1, we have that |y(t)|<λ for all t< t1. Hence  (t)= y(t) and z(t) = 0 for all t<t1. At t=t1, let |y(t)| cross λ. If y(t1)>λ, then Comp-1 triggers a positive value. Else if, y(t1)<λ, Comp-2 triggers a negative value. The DVG is designed such that for each positive input value, its output signal level increases by -2λ, whereas, for a negative input value, it decreases its output voltage by 2λ. Precisely, this task in the hardware is realized by using an up/down counter, a Digital-to-Analog Converter (DAC), a multiplexer (MUX), and a multiplier M, as depicted in Figure 5. Hence, in the current example, DVG generates a signal z(t) = sgn((t1 ))2λ u(t-t1) where u(t) is the unit-step function. In this way, by adding or subtracting constant DC signals from y(t) whenever it crosses the DR [-λ, λ], the amplitude levels of yλ (t) are kept within the ADC's DR. 

Board and Its Specifications:

 

Specifications:

  • Is designed to perform folding prior to the sampler. Thus, it utilizes faster ADCs with shorter hold times
  • Can handle signals with DR of [−11.75𝑉,11.75𝑉].
  • Has a DR of [−1.25,1.25]. Hence, the hardware can fold signals that are eight times larger than the DR of the ADC.                                                                  

Graphical User Interface:

 

 

 

Hardware Results:

Performance Comparison:

  •     B2 R2 demonstrates robustness and operates at slightly above the Nyquist rate. However, it is not computationally efficient

  •     LASSO- B2 R2 is faster and robust, but requires a high sampling rate for lower λ values

3. Conclusions

  • This demo addressed the high DR issue of an ADC using the non-linear modulo operator.
  • We proposed two recovery algorithms.
  • We designed a hardware prototype for modulo operation, which can handle signals up to 10 KHz

 

for more Green Data Acquisition: https://www.weizmann.ac.il/math/yonina/green-data-acquisition

4. References

1] S. B. Shah, S. Mulleti and Y. C. Eldar, “Lasso-Based Fast Residual Recovery For Modulo Sampling", in IEEE Int. Conf. Acoust., Speech and Signal Process (ICASSP), , pp. 1-5, 2023

[2] E.Azar, S. Mulleti, and Y. C. Eldar, “Residual Recovery Algorithm For Modulo Sampling", in IEEE Int. Conf. Acoust., Speech and Signal Process. (ICASSP), 2022, pp. 5722–5726.

[3] S. Mulleti, E. Azar, S. B. Shah, N. Glazer, S. Savariego, O. Cohen, E. Reznitskiy, M. Namer, and Y. C. Eldar, “Hardware demonstration of low-rate and high-dynamic range ADC,” in Show and Tell Demo., IEEE Int. Conf. Acoust., Speech and Signal Process. (ICASSP), 2022.

[4] S. Mulleti, E. Reznitskiy, S. Savariego, M. Namer, N. Glazer and Y. C. Eldar, “A hardware prototype of wideband high-dynamic range analog-to-digital converter”. IET Circuits Devices Syst. 17(4), 181–192, 2023.

[5] E. Azar, S. Mulleti and Y. C. Eldar, "Robust Unlimited Sampling Beyond Modulo", arXiv preprint arXiv:2206.14656, June 2022.

5. Videos

ICASSP 2022

 

ICASSP 2021